TOKYO, JAPAN -- Tokyo Electron Limited (TEL; Head Office: Minato-ku, Tokyo; CEO, President: Tetsuro Higashi) and Teseda Corporation (Head Office: Portland, Oregon; President and CEO: Steve Morris) are announcing today an integrated system which enables low cost of ownership (COO) by using Design For Testability (DFT).

In recent years, with the increasing integration and functionality of System on a Chip (SoC) devices, the cost and time required for testing and test development have become major obstacles. The amount of test data required to provide high quality tests has grown to the extent that it is impossible to generate it manually and still meet time-to-market constraints. To overcome these difficulties, automated test generation techniques based on DFT methodologies have entered the mainstream. However, test cells (test systems) specializing in DFT for wafer testing have not been available to this point.

The demonstration system consists of the Wafer Prober P-8XL from TEL, a leading supplier of wafer probers and other test cells, and the Validator 500? from Teseda, a supplier of DFT-focused validation systems that achieves a test cost of less than $200 per pin. The combined system enables wafer tests on devices (semiconductor chips) equipped with DFT circuits, making it possible to reduce both test costs and test design man-hours.

Yoshinori ("Cat") Inoue, General Manager of TEL's Test System Business Unit, said, "A wide range of TEL customers are currently using DFT, and it has been proven to provide high test quality and realize time reduction effects. We will work with Teseda to develop test solutions with the aim of helping customers to pursue DFT advantages and reduce wafer-level test costs."

Steve Morris, Teseda's president and CEO, said, "I'm very happy that Teseda has been selected as a partner for TEL's wafer-level DFT validation systems. The DFT 'cell-demo' validation system eliminates the need for wafer package cycle latency time. I look forward to working with TEL to develop other DFT test applications in the future as well."

The companies will carry out a demonstration to prove the concept of the DFT validation system at SEMICON Europa 2003 to be held in Munich beginning April 1.