Tokyo Electron (TEL) today announced the joint development with IBM of a novel Tunable Etch-Resistant Anti-Reflective Coating (TERA), a dielectric film with complementary anti-reflective (ARC) and hard mask properties that enables high-resolution CMOS device patterning at the 65nm technology node and beyond.

CMOS device patterning at the 65nm node will likely require the use of antireflective coatings and ever-thinner photoresist films to improve process latitude, especially when coupled with high numerical aperture (NA) optical exposure tools. However, thinning the photoresist can compromise the ability of the resist to accurately transfer the lithographic pattern into the underlying film during a subsequent etch process. This is of particular concern as aggressive resist trim processes are implemented to reduce the critical dimension of the transistor gate. To address this, device manufacturers may incorporate a sacrificial hard mask film under the photoresist/ARC stack to improve pattern transfer and resolution during the etch process. IBM and TEL developed the TERA process to address the issues associated with nanometer-scale CMOS transistor gate fabrication.

TERA is a silicon-based material deposited by plasma-enhanced chemical vapor deposition (PECVD). Extremely high reflectivity control can be engineered into the film, resulting in near zero reflectance at the resist/TERA interface. TERA's optical properties may also be tuned for optimum performance with a variety of photoresists and underlying films. The superior antireflective properties of TERA significantly improve the resolution and latitude of the lithographic process compared to conventional ARC films. This is particularly important as the industry moves to high-resolution scanners that incorporate high numerical aperture optics. In addition, TERA provides better etch selectivity to photoresist than can be attained with conventional ARCs and has built-in hard mask properties for silicon and dielectric etching processes. The TERA material can also be removed by a proprietary stripping process, which simplifies integration into the gate patterning module. These benefits of TERA improve the resolution and performance of 193nm optical lithography.

The TERA material and process were invented by members of the Advanced Lithography Group at IBM's Thomas J. Watson Research Center in Yorktown Heights, N.Y. The process was adapted for use on TEL's dielectric CVD chamber, a highly refined plasma deposition system that has been under development for several years. The dielectric CVD process chamber is integrated with TEL's production-proven Trias™ platform. A 300mm tool was delivered to IBM's state-of-the-art facility in East Fishkill, N.Y.

"The nanometer era of device fabrication has presented unprecedented challenges to our industry", said T.C. Chen, IBM Fellow and Vice President of Science and Technology, IBM Research. "Strong relationships between device manufacturers like IBM and equipment suppliers like TEL are essential in bringing enabling technology from research to manufacturing."

Ryuichi Komatsubara, TEL Senior Vice President of Technology and Marketing added, "IBM has a long history of introducing new and enabling materials to our industry. TEL is pleased at the opportunity to work with IBM on this development effort, as it has clearly proven to be a win-win situation for both our companies."

About IBM Microelectronics

IBM Microelectronics is a key contributor to IBM's role as the world's premier information technology supplier. It develops, manufactures and markets state-of-the-art semiconductor and interconnect technologies, products and services. IBM Microelectronics activities are focused in three major areas: custom application specific integrated circuit (ASIC) chips, PowerPC-based standard chip products, and high-tech foundry services. Its superior integrated solutions can be found in many of the world's best-known electronic brands.

IBM is a recognized innovator in the chip industry, having been first with advances like more power-efficient copper wiring in place of aluminum and faster silicon-on-insulator (SOI) and silicon germanium transistors. These and other innovations have contributed to IBM's standing as the number one U.S. patent holder for 10 consecutive years. More information about IBM Microelectronics can be found at: http://www.ibm.com/chips.